1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device with elements isolated by an insulating film.
2. Description of the Prior Art
Recent efforts which have been made to fabricate highly integrated semiconductor devices have been accompanied by attempts to reduce gate dimensions of MOS transistors and device dimensions such as aluminum interconnection widths, and also to reduce element isolation area widths with greater importance. Processes for isolating elements with grooves or selective epitaxy are well known in the art for semiconductor devices having a high element density.
One conventional process of diffusion in a groove is to introduce an impurity into the side walls of the groove as disclosed in Japanese laid-open patent publication No. 63-37631.
FIG. 2 of the accompanying drawings shows a structure for suppressing a leakage current in the side walls of a groove as disclosed in Japanese laid-open patent publication No. 21210/94. FIGS. 1a through 1g of the accompanying drawings show in cross section sequential steps of a process for manufacturing the semiconductor device disclosed in Japanese laid-open patent publication No. 21210/94.
The manufacturing process shown in FIGS. 1a through 1g will be described below. As shown in FIG. 1a, a silicon oxide film 2 having a thickness of about 20 nm is formed as a first insulating film 2 on a p-type silicon substrate 1 by thermal oxidization, and then a polycrystalline silicon film 3 having a thickness of about 200 nm is deposited as a first polycrystalline silicon film on the silicon oxide film 2 by chemical vapor deposition (CVD). Thereafter, a CVD silicon oxide film 14 having a thickness of about 100 nm is deposited as a second insulating film on the polycrystalline silicon film 3, following which a polycrystalline silicon film 15 having a thickness of about 100 nm is deposited as a second polycrystalline silicon film on the silicon oxide film 14. A photoresist 4 is then deposited on the polycrystalline silicon film 15 to cover areas other than an element isolation area.
Thereafter, using the photoresist 4 as a mask, portions of the polycrystalline silicon film 15, the silicon oxide film 14, and the polycrystalline silicon film 3 are successively etched away, thus forming an opening with the silicon oxide film 2 exposed at the bottom thereof. Using the photoresist 4 also as a mask, ions of boron are injected into the surface of the p-type silicon substrate 1 at, for example, 1.0.times.10.sup.13 cm.sup.-2 at 30 KeV, forming a p.sup.+ -diffusion layer 5 (see FIG. 1b) in the surface of the silicon substrate 1 immediately below the opening. Thereafter, the photoresist 4 is removed.
As shown in FIG. 1c, a CVD silicon oxide film 6 having a thickness of about 100 nm is deposited as a third insulating film over the entire area of the polycrystalline silicon film 15.
The silicon oxide film 6 is then anisotropically etched to expose the upper surface of the polycrystalline silicon film 15, with a spacer being left composed of a CVD silicon oxide film 6a on the side walls of the opening as shown in FIG. 1d. At the same time, a portion of the silicon oxide film 2 which is not covered with the spacer is removed from the bottom of the opening, so that a p.sup.+ -diffusion layer 5 is exposed which is self-aligned with the spacer.
Thereafter, the silicon substrate 1 is subjected to anisotropic etching to form a groove 7 (see FIG. 1e) having a depth of about 0.5 .mu.m, the groove 7 extending through the p.sup.+ -diffusion layer 5 and being self-aligned with the spacer. Simultaneously, the polycrystalline silicon film 15 is removed. Boron ions are injected perpendicularly into the surface of the p-type silicon substrate 1 at, for example, 1.0.times.10.sup.13 cm.sup.-2 at 30 KeV, forming a p.sup.+ -diffusion layer 5a in the bottom of the opening. A CVD silicon oxide film 8 having a thickness of about 1 .mu.m is then deposited as a fourth insulating film over the entire surface formed thus far.
The silicon oxide films 8, 14 are etched back until the upper surface of the polycrystalline silicon film 3 is exposed. The silicon oxide film 14 is now completely removed. The groove 7 is filled with the CVD silicon oxide film 8, which is joined to the spacer composed of a CVD silicon oxide film 6b (see FIG. 1f).
The polycrystalline silicon film 3 is then etched away. As shown in FIG. 1g, the groove 7 is filled with the silicon oxide film 8 as an insulating film, the p.sup.+ -diffusion layer 5a being self-aligned with the groove 7. The silicon oxide films 8, 6b jointly provide a thick insulating film in and above the groove 7, for thereby suppressing a small leakage current along the groove 7.
The semiconductor device thus manufactured according to the process steps shown in FIGS. 1a through 1g is illustrated in FIG. 2.
An element isolation structure produced by selective epitaxy as disclosed in Japanese laid-open patent publication No. 224242/85 is shown in FIG. 3 of the accompanying drawings.
The element isolation structure shown in FIG. 3 is fabricated as follows: As shown in FIG. 3, a silicon oxide film 6 having a thickness of about 2 .mu.m is formed on a p-type silicon substrate 1, and thereafter an area other than an element isolation area is etched away.
Subsequently, a silicon film is grown to a thickness of 2 .mu.m on the surface of the silicon substrate 1 according to epitaxial growth, thus providing an epitaxial layer 13, and a transistor is formed therein. To form flat portions of the epitaxial layer 13, the silicon substrate 1 has a (100) face, and a pattern for etching away the thermally oxidized film is formed parallel to the (100) face.
The conventional semiconductor device shown in FIG. 2 is fabricated simply by introducing an impurity into the side walls of the groove. Such a process is disadvantageous in that it fails to suppress a leakage current along the side walls if an interconnection is positioned in an upper layer thereof. A small leakage current is suppressed by a structure in which the p.sup.+ -diffusion layer is self-aligned with the groove and the thick insulating film is provided in and above the groove. However, such a structure is also problematic because as the source/drain n.sup.+ -diffusion layer of a transistor is held in contact with the p.sup.+ -diffusion layer, attempts to increase the density of the p.sup.+ -diffusion layer and to minimize the small leakage current result in a reduction in the junction dielectric strength. Since the thick insulating film has vertical side walls, they will remain unremoved and cause a short circuit or increase the gate capacitance when a material of a gate electrode of a transistor is subsequently patterned.
The element isolation structure produced by selective epitaxy shown in FIG. 3 is also disadvantageous in that the junction leakage current is large because the source/drain n.sup.+ -diffusion layer is formed in a facet.